The present invention relates to multi-function semiconductor structures and, in particular, a semiconductor structure capable of bipolar and/or field effect transistor function formed using silicon on insulator (SOI) technology.
It is known how to produce field effect transistors (FETs) and bipolar transistors which are topologically separated on a semiconductor substrate. In BiCMOS, for example, groups of insulated gate n- and p-channel transistors (CMOS transistor), associated with an npn bipolar transistor, are formed on the same silicon chip. These transistors are arranged side-by-side and completely isolated from one another.
Advances in SOI technology have opened the door to many new device designs for both bipolar and field effect transistors. In SOI, a layer of semiconductor material is formed on a layer of an insulator. The device regions are formed within the semiconductor material overlying the insulator. Therefore, the high junction capacitance associated with bulk silicon technology is significantly decreased with SOI.
The use of SOI has advanced the development of multi-function semiconductor structures. For example, in U.S. Pat. No. 5,552,624 to Skotnicki et al., a multi-function semiconductor structure formed in SOI and exhibiting negative dynamic resistance is described. This structure includes, topologically integrated within the same semiconductor structure, a first semiconductor area capable of forming an insulated gate field effect transistor and a second semiconductor area capable of forming a lateral bipolar transistor. The two areas have a common semiconductor layer in which the channel of the field effect transistor capable of being formed and/or the base current of the bipolar transistor is capable of flowing. These two areas are capable of forming a negative dynamic resistance structure. The dynamic resistance effect is achieved by spreading a depletion region from the gated top surface of the semiconductor layer. This, in turn, increases the base resistance. However, in Skotnicki et al., the source diffusion extends all the way to the back interface between the semiconductor material and the insulator, making it impossible to completely pinch off the connection to, that is isolate, the base. Therefore, a lateral leakage path exists through a portion of the source/drain regions which are not covered by the gate conductor. As a result, the feedback effect is not as pronounced as possible. Additionally, in Skotnicki et al., the gate and source do not overlap. This gated structure thus does not function well as an FET as is claimed in Skotnicki et al., but as a trigger for the negative dynamic resistance.
Thus, there is a need for a multi-function semiconductor structure which can operate as either an FET or a bipolar transistor or as both an FET and bipolar transistor simultaneously.
A multi-function semiconductor structure in which an FET and a bipolar transistor are formed and methods of forming the same, are provided. A combined FET/bipolar device comprises a semiconductor substrate formed on an insulating layer. A source/emitter region and a drain region are formed in the semiconductor substrate bordering first opposite sides of a body region therebetween. A gate is formed above the substrate between the source/emitter region and the drain region to form an FET having three terminals including the gate, the source/emitter region, and the drain region. A base region is provided in the substrate. A collector region is formed in the substrate abutting the drain region and extending further under the gate than the drain region. This forms a bipolar transistor having three terminals including the base region, the source/emitter region, and the collector region. The shortest distance between the collector region and the source/emitter region defines a base width.
In one method of forming a combined FET/bipolar device, a semiconductor material is provided on an insulator. A gate region is defined on the semiconductor material using a mask. Spacers are formed on the semiconductor material in the gate region and on ends of the mask. One of the spacers is removed and a foot implant is formed in the semiconductor material extending under the gate region. The remaining spacer is removed and a halo, having an opposite conductivity type as the foot implant, is implanted into the semiconductor material.
According to another method of forming a combined FET/bipolar transistor, a semiconductor material is provided on an insulating layer. A collector region formed in the semiconductor material adjacent to the insulating layer. A gate structure is formed on the semiconductor material. Source/emitter and drain regions are formed in the semiconductor material on opposite sides of the gate structure. Halos of an opposite conductivity type as the collector region are formed between the source/emitter region and the collector region and between the drain region and the collector region. A reach through implant of the same conductivity type as the collector region is formed on the drain side of the gate structure to counter-dope the halo and connect the drain region to the collector region.